This is defined by the clock configuration you have selected with the oscillator, PLL and peripheral clock divisors you have selected in the configuration words and your initialization code. The maximum frequency of the PWM is based on the FCYC clock of the dsPIC. At the very simplest it is the value to set in the PR2 (or PR3 if the PWM is using TIMER3) register plus 1 converted to bits using the formula LOG(PR2+1)/LOG2. For the dsPICs and PIC24s it is the ratio of the TIMER input clock frequency to PWM output frequency. The basic concept of duty cycle resolution remains the same. The PWM function blocks in the dsPICs and PIC24s are different from the one in the PIC18F. The highest PWM frequency with 10-bits of resolution is: (FOSC/1020), PR2=255, TIMER2 prescaler 1:1. The lowest available hardware controlled PWM frequency is (FOSC/16320), PR2=255, TIMER2 prescaler 16:1, resolution is 10 bits. Using the method you can enumerate all valid PWM duty cycles for the PWM period set by TIMER2 then use the formula LOG(n)/LOG(2) to find the number of bits of resolution. The maximum PWM frequency is obtained when the PR2 register is set to ZERO with the TIMER2 prescaler set to 1:1, this yields a PWM frequency of (FOSC/4) and a duty cycle resolution of 2-bits.ĭuty cycle of 0%, CCPxL = 0x00, CCPxCON = 0, CCPxCON = 0.ĭuty cycle of 25%, CCPxL = 0x00, CCPxCON = 0, CCPxCON = 1.ĭuty cycle of 50%, CCPxL = 0x00, CCPxCON = 1, CCPxCON = 0.ĭuty cycle of 75%, CCPxL = 0x00, CCPxCON = 1, CCPxCON = 1.ĭuty cycle of 100%, CCPxL = 0x01, CCPxCON = 0, CCPxCON = 0.Īny values of CCPxL greater than the value in PR2 will yield a 100% (always high) PWM output. Capacitively couple the output of the filter into an audio amplifier, such as an LM386, then into a loudspeaker of some sort.įor a PIC18F the bounds of duty cycles resolution must be between 2-bits and 10-bits.Īnother way to express this resolution is to count how many different values can the CCPxL+CCPxCON bits be set with some affect on the pulse width of the PWM output for the period set in the TIMER2 register PR2. However, dsPICs have a lot of flash memory, so the chip itself might be good enough.Īttach a 4 kohm resistor and a 0.01 uF (10 nF) capacitor to the output pin. Storage of audio of any decent length might require an external IC, such as a dataflash. In the timer's ISR, grab a new sample from the stored audio and put it into the Duty Cycle register of the peripheral. Setup another timer to interrupt at a rate equivalent to the audio sample rate in your case, 8 kHz. In a dsPIC, usually this will be either TMR2 or TMR3. One timer will be the timebase for the Output Compare peripheral. The Output Compare setup will require two timers. OC module frequency = Fpwm = (Ftmr) / (10^(R*log(2))) The lower the resolution, the higher the speed.Ĭomputing the PWM frequency for a given resolution: The advantage of the lowest resolution possible is that an inverse relationship exists between speed and resolution. The PIC18F architecture uses the actual oscillator frequency, not the instruction clock. OC module resolution = log(Tpwm/Ttmer) / log(2) = log(Ftmr/Fpwm) / log(2) PWM module resolution = log((2*Tpwm)/Tcy) / log(2) = log((2*Fcy)/Fpwm) / log(2) Since modern-day microcontrollers are so fast, you can really jack the clock rate high enough to get the PWM frequency well into the attenuation band of the simple filter. Going into the active filter realm greatly complicates the hardware side of the design. First off, one can approach this problem from one of two basic perspectives:ġ) emphasize the sophistication of the filter in order to keep the ripple downĢ) go with a simple R-C filter and jack the PWM frequency as high as possible above the sampling rate
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